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QL4009 QuickRAM Data Sheet
* * * * * * 9,000 Usable PLD Gate QuickRAM ESP Combining Performance,
Density and Embedded RAM
Device Highlights
High Performance & High Density
* 9,000 Usable PLD Gates with 82 I/Os * 300 MHz 16-bit Counters, 400 MHz
Advanced I/O Capabilities
* Interfaces with both 3.3 V and 5.0 V devices * PCI compliant with 3.3 V and 5.0 V busses
Datapaths, 160+ MHz FIFOs * 0.35 m four-layer metal non-volatile CMOS process for smallest die sizes
for -1/-2/-3/-4 speed grades * Full JTAG boundary scan * I/O Cells with individually controlled Registered Input Path and Output Enables
High Speed Embedded SRAM
* 8 dual-port RAM modules, organized in
user-configurable 1,152 bit blocks * 5 ns access times, each port independently accessible * Fast and efficient for FIFO, RAM, and ROM functions
8 RAM Blocks
160 High Speed Logic Cells
Easy to Use / Fast Development Cycles
* 100% routable with 100% utilization and
Interface
complete pin-out stability * Variable-grain logic cells provide high performance and 100% utilization * Comprehensive design tools include high quality Verilog/VHDL synthesis
Figure 1: QuickRAM Block Diagram
(c) 2002 QuickLogic Corporation
www.quicklogic.com
* * * * * *
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QL4009 QuickRAM Data Sheet Rev B
Architecture Overview
The QuickRAMTM family of ESPs (Embedded Standard Products) offers FPGA logic in combination with Dual-Port SRAM modules. The QL4009 is a 9,000 usable PLD gate member of the QuickRAM family of ESPs. QuickRAM ESPs are fabricated on a 0.35m four-layer metal process using QuickLogic's patented ViaLinkTM technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. The QL4009 contains 160 logic cells and 8 Dual Port RAM modules (see Figure 1). Each RAM module has 1,152 RAM bits, for a total of 9,216 bits. RAM Modules are Dual Port (one read port, one write port) and can be configured into one of four modes: 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 (see Figure 4). With a maximum of 82 I/Os, the QL4009 is available in 68-pin PLCC, 84-pin PLCC and 100-pin TQFP packages. Designers can cascade multiple RAM modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules (see Figure 2). This approach allows up to 512-deep configurations as large as 16 bits wide in the smallest QuickRAM device and 44 bits wide in the largest device. Software support for the complete QuickRAM family, including the QL4009, is available through two basic packages. The turnkey QuickWorksTM package provides the most complete ESP software solution from design entry to logic synthesis, to place and route, to simulation. The QuickToolsTM packages provides a solution for designers who use Cadence, Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Aldec, or other third-party tools for design entry, synthesis, or simulation. The QuickLogic variable grain logic cell features up to 16 simultaneous inputs and 5 outputs within a cell that can be fragmented into 5 independent cells. Each cell has a fan-in of 29 including register and control lines (see Figure 3).
WDATA
RAM Module (1,152 bits)
RDATA
WADDR
RADDR
RAM Module (1,152 bits) WDATA RDATA
Figure 2: QuickRAM Module Bits
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(c) 2002 QuickLogic Corporation
QL4009 QuickRAM Data Sheet Rev B
Product Summary
Total of 82 I/O Pins
* 74 bi-directional input/output pins, PCI-compliant for 5.0 V and 3.3 V buses for
-1/-2/-3/-4 speed grades * 8 high-drive input/distributed network pins
Eight Low-Skew Distributed Networks
* Two array clock/control networks available to the logic cell flip-flop clock, set and reset
inputs - each driven by an input-only pin * Six global clock/control networks available to the logic cell F1, clock, set and reset inputs and the input and I/O register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or I/O pin, or any logic cell output or I/O cell feedback
High Performance Silicon
* Input + logic cell + output total delays under 6 ns * Data path speeds over 400 MHz * Counter speeds over 300 MHz * FIFO speeds over 160+ MHz
(c) 2002 QuickLogic Corporation
www.quicklogic.com * *
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QL4009 QuickRAM Data Sheet Rev B
AC Characteristics at VCC = 3.3 V, TA = 25 C (K = 1.00)
To calculate delays, multiply the appropriate K factor from Table 10: Operating Range by the following numbers in the tables provided.
QS A1 A2 A3 A4 A5 A6 QS OP B1 B2 C1 C2 MP MS D1 D2 E1 E2 NP NS F1 F2 F3 F4 F5 F6 QC QR
AZ
OZ QZ
NZ
FZ
Figure 3: QuickRAM Logic Cell
Table 1: Logic Cell Symbol Parameter 1 tPD tSU tH tCLK tCWHI tCWLO tSET tRESET tSW tRW Combinatorial Delaya Setup Time Hold Time Clock to Q Delay Clock High Time Clock Low Time Set Delay Reset Delay Set Width Reset Width
a
Propagation Delays (ns) Fanout (5) 2 1.7 1.7 0.0 1.0 1.2 1.2 1.3 1.1 1.9 1.8 3 1.9 1.7 0.0 1.2 1.2 1.2 1.5 1.3 1.9 1.8 4 2.2 1.7 0.0 1.5 1.2 1.2 1.8 1.6 1.9 1.8 5 3.2 1.7 0.0 2.5 1.2 1.2 2.8 2.6 1.9 1.8
1.4 1.7 0.0 0.7 1.2 1.2 1.0 0.8 1.9 1.8
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of your particular design.
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QL4009 QuickRAM Data Sheet Rev B
[8:0] [17:0]
WA WD WE WCLK
RE RCLK RA RD ASYNCRD [8:0] [17:0]
[1:0]
MODE
Figure 4: QuickRAM Module
Table 2: RAM Cell Synchronous Write Timing Symbol Parameter 1 tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA Setup Time to WCLK WA Hold Time to WCLK WD Setup Time to WCLK WD Hold Time to WCLK WE Setup Time to WCLK WE Hold Time to WCLK WCLK to RD (WA=RA)
a
Propagation Delays (ns) Fanout 2 1.0 0.0 1.0 0.0 1.0 0.0 5.3 3 1.0 0.0 1.0 0.0 1.0 0.0 5.6 4 1.0 0.0 1.0 0.0 1.0 0.0 5.9 5 1.0 0.0 1.0 0.0 1.0 0.0 7.1
1.0 0.0 1.0 0.0 1.0 0.0 5.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25 C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
Table 3: RAM Cell Synchronous Read Timing Symbol Logic Cells tSRA tHRA tSRE tHRE tRCRD RA Setup Time to RCLK RA Hold Time to RCLK RE Setup Time to RCLK RE Hold Time to RCLK RCLK to RDa Parameter 1 1.0 0.0 1.0 0.0 4.0 Propagation Delays (ns) Fanout 2 1.0 0.0 1.0 0.0 4.3 3 1.0 0.0 1.0 0.0 4.6 4 1.0 0.0 1.0 0.0 4.9 5 1.0 0.0 1.0 0.0 6.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25 C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
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QL4009 QuickRAM Data Sheet Rev B
Table 4: RAM Cell Asynchronous Read Timing Symbol Parameter 1 RPDRD RA to RDa 3.0 Propagation Delays (ns) Fanout 2 3.3 3 3.6 4 3.9 5 5.1
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25 C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
Table 5: Input-Only / Clock Cells Symbol Parameter 1 tIN tINI tISU tIH tICLK tIRST tIESU tIEH High Drive Input Delay High Drive Input, Inverting Delay Input Register Set-Up Time Input Register Hold Time Input Register Clock To Q Input Register Reset Delay Input Register Clock Enable Setup Time Input Register Clock Enable Hold Time Propagation Delays (ns) Fanout 2 3 4 8 12 24
1.5 1.6 1.8 1.9 2.4 2.9 4.4 1.6 1.7 .19 2.0 2.5 3.0 4.5 3.1 3.1 3.1 3.1 3.1 3.1 3.1 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.7 0.8 1.0 1.1 1.6 2.1 3.6 0.6 0.7 0.9 1.0 1.5 2.0 3.5 2.3 2.3 2.3 2.3 2.3 2.3 2.3 0.0 0.0 0.0 0.0 0.0 0.0 0.0
Table 6: Clock Cells Symbol Parameter 1 tACK tGCKP tGCKB Array Clock Delay Global Clock Pin Delay Global Clock Buffer Delay Propagation Delays (ns) Fanouta 2 3 4 8 10 11
1.2 1.2 1.3 1.3 1.5 1.6 1.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.8 0.8 0.9 0.9 1.1 1.2 1.3
a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay. The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column.
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QL4009 QuickRAM Data Sheet Rev B
Table 7: I/O Cell Input Delays Symbol Parameter 1 tI/O tISU tIH tIOCLK tIORST tIESU tIEH Input Delay (bidirectional pad) Input Register Set-Up Time Input Register Hold Time Input Register Clock to Q Input Register Reset Delay Input Register Clock Enable Set-Up Time Input Register Clock Enable Hold Time 1.3 3.1 0.0 0.7 0.6 2.3 0.0 Propagation Delays (ns) Fanouta 2 1.6 3.1 0.0 1.0 0.9 2.3 0.0 3 1.8 3.1 0.0 1.2 1.1 2.3 0.0 4 2.1 3.1 0.0 1.5 1.4 2.3 0.0 8 3.1 3.1 0.0 2.5 2.4 2.3 0.0 10 3.6 3.1 0.0 3.0 2.9 2.3 0.0
a. Stated timing for worst case Propagation Delay over process variation at VCC = 3.3 V and TA = 25 C. Multiply by the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
Table 8: I/O Cell Output Delays Symbol Parameter 3 tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ Output Delay Low to High Output Delay High to Low Output Delay Tri-state to High Output Delay Tri-state to Low Output Delay High to Tri-state
a
Propagation Delays (ns) Output Load Capacitance (pF) 50 2.5 2.6 1.7 2.0 75 3.1 3.2 2.2 2.6 100 3.6 3.7 2.8 3.1 150 4.7 4.8 3.9 4.2 -
2.1 2.2 1.2 1.6 2.0 1.2
Output Delay High to Tri-statea
a. The following loads are used for tPXZ
tPHZ 1 5 pF
1 tPLZ 5 pF
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QL4009 QuickRAM Data Sheet Rev B
DC Characteristics
The DC specifications are provided in the tables below.
Table 9: Absolute Maximum Ratings Parameter VCC Voltage VCCIO Voltage Input Voltage Latch-up Immunity Value -0.5 to 4.6 V -0.5 to 7.0 V -0.5 V to VCCIO +0.5 V 200 mA Parameter DC Input Current ESD Pad Protection Storage Temperature Lead Temperature Value 20 mA 2000V -65 C to +150 C 300 C
Table 10: Operating Range Symbol Parameter Military Min VCC VCCIO TA TC Supply Voltage I/O Input Tolerance Voltage Ambient Temperature Case Temperature -0 Speed Grade -1 Speed Grade K Delay Factor -2 Speed Grade -3 Speed Grade -4 Speed Grade 3.0 3.0 -55 0.42 0.42 0.42 Max 3.6 5.5 125 2.03 1.64 1.37 Industrial Min 3.0 3.0 -40 0.43 0.43 0.43 0.43 0.43 Max 3.6 5.5 85 1.90 1.54 1.28 0.90 0.82 Commercial Min 3.0 3.0 0 0.46 0.46 0.46 0.46 0.46 Max 3.6 5.25 70 1.85 1.50 1.25 0.88 0.80 V V C C n/a n/a n/a n/a n/a Unit
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QL4009 QuickRAM Data Sheet Rev B
Table 11: DC Characteristics Symbol VIH VIL VOH Parameter Input HIGH Voltage Input LOW Voltage Output HIGH Voltage IOH = -12 mA IOH = -500 A IOL = 16 mAa IOL = 1.5 mA VI = VCCIO or GND VI = VCCIO or GND -10 -10 Conditions Min 0.5VCC -0.5 2.4 0.9VCC 0.45 0.1VCC 10 10 10 VO = GND VO = VCC VI, VIO = VCCIO or GND -15 40 0.50 (typ) 0 -180 210 2 100 Max VCCIO+0.5 0.3VCC Units V V V V V V A A pF mA mA mA A
VOL II IOZ CI IOS ICC ICCIO
Output LOW Voltage I or I/O Input Leakage Current 3-State Output Leakage Current Input Capacitanceb Output Short Circuit Currentc D.C. Supply Current
d
D.C. Supply Current on VCCIO
a. Applies only to -1/-2/-3/-4 commercial grade devices. These speed grades are also PCI-compliant. All other devices have 8 mA IOL specifications. b. Capacitance is sample tested only. Clock pins are 12 pF maximum. c. Only one output at a time. Duration should not exceed 30 seconds. d. For -1/-2/-3/-4 commercial grade devices only. Maximum ICC is 3 mA for -0 commercial grade and all industrial grade devices. and 5 mA for all military grade devices. For AC conditions, contact QuickLogic customer applications group.
(c) 2002 QuickLogic Corporation
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QL4009 QuickRAM Data Sheet Rev B
Kv and Kt Graphs
Voltage Factor vs. Supply Voltage
1.1000 1.0800 1.0600 1.0400
Kv
1.0200 1.0000 0.9800 0.9600 0.9400 0.9200 3 3.1 3.2 3.3 3.4 3.5 3.6
Supply Voltage (V)
Figure 5: Voltage Factor vs. Supply Voltage
Temperature Factor vs. Operating Temperature
1.15 1.10 1.05 1.00 0.95 0.90 0.85 -60 -40 -20 0 20 40 60 80
Kt
Junction Temperature C
Figure 6: Temperature Factor vs. Operating Temperature
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QL4009 QuickRAM Data Sheet Rev B
Power-up Sequencing
VCCIO
Voltage
VCC (VCCIO -VCC)MAX VCC
400 us
Time
Figure 7: Power-up Requirements
The following requirements must be met when powering up the device: (Refer to Figure 7 above) this recommendation can cause permanent damage to the device. * VCCIO must lead VCC when ramping the device. * The power supply must take greater than or equal to 400 s to reach VCC. Ramping to VCC/VCCIO earlier than 400 s can cause the device to behave improperly. An internal diode is present in-between VCC and VCCIO, as shown in Figure 8.
V CC V CCIO
* When ramping up the power supplies keep (VCCIO -VCC)MAX 500 mV. Deviation from
Internal Logic Cells, RAM blocks, etc
IO Cells
Figure 8: Internal Diode Between VCC and VCCIO
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QL4009 QuickRAM Data Sheet Rev B
JTAG
TCK TMS TRSTB TAp Controller State Machine (16 States) Instruction Decode & Control Logic
Instruction Register
RDI
Mux Boundary-Scan Register (Data Register)
Mux
TDO
Bypass Register
Internal Register
I/O Registers
User Defined Data Register
Figure 9: JTAG Block Diagram
Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design challenges, not the least of which concerns the accessibility of test points. The Joint Test Access Group (JTAG) formed in response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR); these allow users to run three required tests, along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements.
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QL4009 QuickRAM Data Sheet Rev B
The 1149.1 standard requires the following three tests:
* Extest Instruction. The Extest instruction performs a PCB interconnect test. This test
places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. This instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed via a data scan operation, allowing users to sample the functional data entering and leaving the device. * Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device.
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QL4009 QuickRAM Data Sheet Rev B
Pin Descriptions
Table 12: Pin Descriptions Pin TDI/RSI Function Description
Hold HIGH during normal operation. Connects to serial Test Data In for JTAG /RAM init. PROM data in for RAM initialization. Connect to VCC if Serial Data In unused. Hold LOW during normal operation. Connects to serial Active low Reset for JTAG /RAM PROM reset for RAM initialization. Connect to GND if init. reset out unused. Test Mode Select for JTAG Test Clock for JTAG Hold HIGH during normal operation. Connect to VCC if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCC or ground if not used for JTAG.
TRSTB/RRO
TMS TCK
TDO/RCO STM I/ACLK I/GCLK I I/O VCC VCCIO GND
Connect to serial PROM clock for RAM initialization. Must Test data out for JTAG /RAM init. be left unconnected if not used for JTAG or RAM clock out initialization. Special Test Mode High-drive input and/or array network driver High-drive input and/or global network driver High-drive input Input/Output pin Power supply pin Input voltage tolerance pin Ground pin Must be grounded during normal operation. Can be configured as either or both. Can be configured as either or both. Use for input signals with high fanout. Can be configured as an input and/or output. Connect to 3.3 V supply. Connect to 5.0 V supply if 5 V input tolerance is required, otherwise connect to 3.3 V supply. Connect to ground. Available on 456-PBGA only. Connect to ground plane on PCB if heat sinking desired. Otherwise may be left unconnected.
GND/THERM Ground/Thermal pin
Ordering Information
QL 4009 - 1 PF100 C QuickLogic device QuickRAM device part number Speed Grade 0 = Quick 1 = Fast 2 = Faster 3 = Faster *4 = Wow
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Operating Range C = Commercial I = Industrial M = Military Package Code PL68 = 68-pin PLCC PF84 = 84-pin PLCC PF100 = 100-pin TQFP
* Contact QuickLogic regarding availabliity
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QL4009 QuickRAM Data Sheet Rev B
68 PLCC Pinout Diagram
987 65 43 2 1 68 67 66 65 64 63 62 61
TDO IO IO IO IO VCCIO IO IO GND IO IO IO IO IO IO STM TCK
Figure 10: Top View of 68 Pin PLCC
68 PLCC Pinout Table
Table 13: 68 PLCC Pinout Table
68 PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Function
GND I/O I/O VCCIO I/O I/O I/O I/O TDO I/O I/O I/O I/O GND I/O GCLK/I ACLK/I
68 PLCC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
TDI IO IO IO IO IO IO IO GND IO IO IO VCCIO IO IO TRSTB TMS
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
IO IO IO IO GND IO GCLK/I ACLK/I VCC GCLK/I GCLK/I IO IO IO IO IO IO
QuickRAM QL4009-1PL68C
IO IO IO IO IO IO GCLK/I GCLK/I VCC ACLK/I GCLK/I IO GND IO IO IO IO
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Function
VCC GCLK/I GCLK/I I/O I/O I/O I/O I/O I/O TDI I/O I/O I/O I/O I/O I/O I/O
68 PLCC 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
Function
GND I/O I/O I/O VCCIO I/O I/O TRSTB TMS I/O I/O I/O I/O GND I/O GCLK/I ACLK/I
68 PLCC 52 53 54 55 56 57 58 58 60 61 62 63 64 65 66 67 68
Function
VCC GCLK/I GCLK/I I/O I/O I/O I/O I/O I/O TCK STM I/O I/O I/O I/O I/O I/O
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QL4009 QuickRAM Data Sheet Rev B
84 PLCC Pinout Diagram
11 10 9 87 65 43 2 1 84 83 82 81 80 79 78 77 76 75
TDO IO IO IO IO IO IO VCCIO IO IO IO IO IO GND IO IO VCC IO IO STM TCK
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
84 PLCC Pinout Table
Table 14: 84 PLCC Pinout Table
84 PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function
I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O TDO I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK/I
84 PLCC 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
TDI IO IO VCC IO IO IO GND IO IO IO IO IO VCCIO IO IO IO IO IO TRSTB TMS
IO IO IO IO IO IO IO GND IO GCLK/I ACLK/I GCLK/I GCLK/I VCC IO IO IO IO IO IO IO
QuickRAM QL4009-1PL84C
IO IO IO IO IO IO IO VCC GCLK/I GCLK/I ACLK/I GCLK/I IO GND IO IO IO IO IO IO IO
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
Figure 11: Top View of 84 Pin PLCC
Function
ACLK/I GCLK/I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O TDI I/O I/O VCC I/O I/O I/O GND I/O I/O
84 PLCC 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Function
I/O I/O I/O VCCIO I/O I/O I/O I/O I/O TRSTB TMS I/O I/O I/O I/O I/O I/O I/O GND I/O GCLK/I
84 PLCC 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84
Function
ACLK/I GCLK/I GCLK/I VCC I/O I/O I/O I/O I/O I/O I/O TCK STM I/O I/O VCC I/O I/O GND I/O I/O
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(c) 2002 QuickLogic Corporation
QL4009 QuickRAM Data Sheet Rev B
100 TQFP Pinout Diagram
Pin 1 Pin 76
QuickRAM QL4009-1PF100C
Pin 26
Pin 51
Figure 12: Top View of 100 Pin TQFP
100 TQFP Pinout Table
Table 15: 100 TQFP Pinout Table
100TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Function
I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O
100TQFP 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Function
TDI I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O TRSTB TMS
100TQFP 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Function
I/O I/O I/O I/O I/O I/O I/O I/O GND I/O I ACLK / I VCC I GCLK / I VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O
100TQFP 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Function
TCK STM I/O I/O I/O I/O I/O I/O I/O GND I/O I/O GND I/O I/O I/O VCCIO I/O I/O I/O I/O I/O I/O I/O TDO
(c) 2002 QuickLogic Corporation
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QL4009 QuickRAM Data Sheet Rev B
Contact Information
Telephone: 408 990 4000 (US) 416 497 8884 (Canada) 44 1932 57 9011 (Europe) 49 89 930 86 170 (Germany) 852 8106 9091 (Asia) 81 45 470 5525 (Japan) E-mail: Support: Web site: info@quicklogic.com support@quicklogic.com http://www.quicklogic.com/
Revision History
Table 16: Revision History Revision A B Date 5/2000 5/2002 Comments First release. Added Kfactor, Power-up, JTAG and mechanical drawing information. Reformatted.
Copyright Information
Copyright (c) 2002 QuickLogic Corporation. All Rights Reserved. The information contained in this product brief, and the accompanying software programs are protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to make periodic modifications of this product without obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic, pASIC, and ViaLink are registered trademarks, and SpDE and QuickWorks are trademarks of QuickLogic Corporation. Verilog is a registered trademark of Cadence Design Systems, Inc.
(c) 2002 QuickLogic Corporation
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